An Efficient I/O Interface Control Block Design Methodology for Application-Specific MPSoC Platforms

In application-specific multiprocessor system-on-a-chips (MPSoC), the complexity of a general-purpose interface control block which implements input/output (I/O) paths for off-chip communication has increased exponentially in recent years. In addition, several inherent issues exist in the design of general-purpose interface control blocks, since many registers and multiple I/O paths are fixed in the relatively late stages of the design, which consequently reduces verification time of the top level. Also, the role of a general-purpose interface control block, which shares a limited number of pins with various IPs, causes frequent changes in pin assignment. This results in many possible human errors when using a traditional RTL description in designing such blocks. In response to this problem, this paper presents a Design Automation-based approach to improve the efficiency and reliability of the design process. In the case study presented, we succeeded in auto-generating a general-purpose interface control block in typical MPSoC platforms with more than 400 general-purpose interfaces including both input and output, as well as 1,200 PAD pins. Ultimately, we reduced the amount of manual description for the generation of a general-purpose interface control block by a whopping 98%.