Effects of voids on bump chip carrier (BCC++) solder joint reliability

Author

Lau, John ; Erasmus, Steve ; Pan, Stephen

Author_Institution

Agilent Technol. Inc., Santa Clara, CA, USA

fYear

2002

fDate

6/24/1905 12:00:00 AM

Firstpage

992

Lastpage

1000

Abstract

In this study, the effects of voids on the solder joint reliability of bump chip carrier (BCC++) packages on a printed circuit board are investigated. Emphasis is placed on the void size, void location, and void percentage. The solder is assumed to obey the Garofalo-Arrhenius creep constitutive equation. A total of 12 different cases are studied. In addition, the effects of voids on the crack growth in the BCC++ solder joint are studied by the fracture mechanics method. Emphasis is placed on the demonstration that a crack in the solder joint may be stopped by a void in front of it.

Keywords

circuit reliability; cracks; finite element analysis; fracture mechanics; integrated circuit packaging; printed circuits; soldering; voids (solid); ANSYS; FEM; Garofalo-Arrhenius creep constitutive equation; PCB; bump chip carrier package; crack growth; finite element code; fracture mechanics method; printed circuit board; solder joint reliability; void effects; void location; void percentage; void size; Creep; Integrated circuit interconnections; Personal digital assistants; Plastic packaging; Printed circuits; Scanning electron microscopy; Soldering; Thermal stresses; X-ray detection; X-ray detectors;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference, 2002. Proceedings. 52nd

ISSN

0569-5503

Print_ISBN

0-7803-7430-4

Type

conf

DOI

10.1109/ECTC.2002.1008222

Filename

1008222