Reuse issues in SoC verification platform

As the VLSI design scale shrinks, traditional verification methods cannot satisfy the SoC verification request, because they do not provide the enough ability to check the function correctness and cannot ensure the product quality. Verification has become the bottleneck of integrated circuit design. A method of bus-based verification platform is presented and the reusability is improved greatly. Issues such as verification platform design, simulation pattern strategies and reuse, as well as IP standalone and SoC verification platforms are discussed. An analysis of the verification platform is performed from the perspective of the reuse across the design cycle, focusing on the IP standalone and the SoC verification platforms.