Title :
A test system architecture to reduce transmission line effects during high speed testing
Author_Institution :
Test Dept., Texas Instrum. Inc., USA
Abstract :
Testing high speed CMOS devices in a “non-terminated” transmission line environment can result in significant timing errors due to signal reflections. These errors can be substantially reduced with a test system designed to minimize the distance between device outputs and tester comparator inputs
Keywords :
CMOS logic circuits; digital simulation; fault diagnosis; logic testing; very high speed integrated circuits; digital signal path; errors; high speed CMOS devices; high speed testing; nonterminated transmission line environment; simulation; test system architecture; tester comparator inputs; timing error; transmission line effects; Automatic testing; Circuit testing; Clamps; Delay effects; Electronic equipment testing; Impedance; Reflection; System testing; Timing; Transmission lines;
Conference_Titel :
Test Conference, 1994. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2103-0
DOI :
10.1109/TEST.1994.528016
