System-on-chip design with dataflow architecture

This work presents a practical approach to implement dataflow dominated system-on-chip system with real-time requirements. With dataflow model and a virtual component (VC)-oriented implementation architecture, the approach has the advantages of effectively supporting design reuse or reconfiguration. Single bus architecture reduces the design complexity and implementation cost and provides an effective way to meet real-time constraints. Based on the architecture some important aspects such as bus arbitrating, VC framework are described, these techniques are critical factors for achieving design goal.