On the design of piecewise regular processor arrays

Consideration is given to the design of a certain class of processor arrays. In comparison to regular arrays, i.e. wavefront or systolic arrays, they may contain context-dependent switching functions, and they can be partitioned into regular subarrays (in time and/or space). The described piecewise affine projection of algorithms on piecewise regular processor arrays fits into the desired hierarchical design approach. Based on mathematical models for piecewise regular algorithms, dependence graphs and processor arrays, a parametric representation for a class of transformation matrices is derived such that the resulting array is guaranteed to have a limited number of essentially different interconnections. In order to optimize the final realization, the methods known for systolic/wavefront arrays can be applied