DocumentCode :
1696732
Title :
On the design of piecewise regular processor arrays
Author :
Thiele, Lothar
Author_Institution :
Inst. of Microelectron., Univ. of Saarlands, Saarbrucken, West Germany
fYear :
1989
Firstpage :
2239
Abstract :
Consideration is given to the design of a certain class of processor arrays. In comparison to regular arrays, i.e. wavefront or systolic arrays, they may contain context-dependent switching functions, and they can be partitioned into regular subarrays (in time and/or space). The described piecewise affine projection of algorithms on piecewise regular processor arrays fits into the desired hierarchical design approach. Based on mathematical models for piecewise regular algorithms, dependence graphs and processor arrays, a parametric representation for a class of transformation matrices is derived such that the resulting array is guaranteed to have a limited number of essentially different interconnections. In order to optimize the final realization, the methods known for systolic/wavefront arrays can be applied
Keywords :
graph theory; matrix algebra; multiprocessor interconnection networks; switching functions; context-dependent switching functions; dependence graphs; hierarchical design approach; multiprocessor networks; piecewise affine projection; piecewise regular processor arrays; regular subarray partition; switching theory; transformation matrices; Algorithm design and analysis; Concrete; Distributed computing; Iterative algorithms; Mathematical model; Microelectronics; Optimization methods; Partitioning algorithms; Pipeline processing; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1989., IEEE International Symposium on
Conference_Location :
Portland, OR
Type :
conf
DOI :
10.1109/ISCAS.1989.100823
Filename :
100823
Link To Document :
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