DocumentCode
1696744
Title
EXECUBE-A New Architecture for Scaleable MPPs
Author
Kogge, Peter M.
Author_Institution
Loral Federal Systems - Owego, USA
Volume
1
fYear
1994
Firstpage
77
Lastpage
84
Abstract
The EXECUBE chip is a new single part type building block for MPP systems that scales seamlessly from a few chips (with a few hundred mips) to thousands of chips with petaop potential. Further, the chip architecture supports directly both SIMD and MIMD modes of processing, permitting not only the best of both current parallel computing modes but also new modes not possible with more conventional designs. This paper discusses the overall architecture of the EXECUBE chip, the new computational model it represents, some comparisons against the current state of the art, how it might be used for real applications, and some extrapolations into future developments.
Keywords
Bandwidth; Computational modeling; Computer architecture; Computer networks; Costs; Extrapolation; Logic design; Network interfaces; Parallel processing; Semiconductor device measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel Processing, 1994. Vol. 1. ICPP 1994. International Conference on
Conference_Location
North Carolina State University, NC, USA
ISSN
0190-3918
Print_ISBN
0-8493-2493-9
Type
conf
DOI
10.1109/ICPP.1994.108
Filename
4115697
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