Title :
A 12 b resolution 200 kFLIPS fuzzy inference processor
Author :
Nakamura, K. ; Sakashita, N. ; Nitta, Y. ; Shimomura, K. ; Ohno, T. ; Eguchi, K. ; Tokuda, T.
Author_Institution :
Mitsubishi Electr. Corp., Hyogo, Japan
Abstract :
A fuzzy inference processor that performs fuzzy inference with 12-b resolution input at 200 kFLIPS (fuzzy logical inferences per second) is described. Three techniques are adopted to attain this performance: (1) membership-function generators constructed of combinational logic, which calculate a membership-function value in less than half of a clock cycle; (2) rule instructions that execute one-rule-by-one instruction in an antecedent unit; and (3) an improved add/divide algorithm that calculates a centroid in a consequent unit. The block diagram of this processor is shown. The chip, fabricated by 1- mu m single-polycide, double-metal CMOS technology, contains 86-k transistors in a 7.5-mm*6.7-mm die, and is packaged in an 80-pin flat package. The chip operates at more than 20-MHz clock frequency at 5 V.<>
Keywords :
CMOS integrated circuits; fuzzy logic; inference mechanisms; microprocessor chips; 1 micron; 12 b resolution; 12 bit; 20 MHz; 5 V; 80-pin flat package; add/divide algorithm; antecedent unit; centroid; combinational logic; consequent unit; double-metal CMOS technology; fuzzy inference processor; membership-function generators; rule instructions; single-polycide; Adders; Clocks; Combinational circuits; Counting circuits; Equations; Logic circuits; Packaging; Pipeline processing; Solid state circuits;
Conference_Titel :
Solid-State Circuits Conference, 1993. Digest of Technical Papers. 40th ISSCC., 1993 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0987-1
DOI :
10.1109/ISSCC.1993.280005