Title :
An 18-34 GHz dynamic frequency divider based on 0.2 mu m AlGaAs/GaAs/AlGaAs quantum-well transistors
Author :
Thiede, A. ; Berroth, M. ; Nowotny, U. ; Seibel, J. ; Bosch, R. ; Kohler, K. ; Raynor, B. ; Schneider, J.
Author_Institution :
Fraunhofer Inst. of Appl. Solid-State Phys., Freiburg, Germany
Abstract :
The design and performance of a dynamic frequency divider operating in the 18-34-GHz range are presented. The schematic of the dynamic frequency divider is shown. Two ring oscillators, each consisting of one SBFL inverter and two source followers, are fed back by transfer gates. A memory type flip-flop is used for data storage during the period when the transfer gates show high resistance due to the low voltage applied to the clock input. The circuit design is optimized by SPICE simulation on the basis of a HEMT (high electron mobility transistor) network model. Measurements on the frequency divider give an 18-GHz lower limit for stable operation. 34 GHz is measured for the maximum input frequency. The pulse diagram of the 34-GHz input and the 17-GHz output is shown.<>
Keywords :
III-V semiconductors; aluminium compounds; field effect integrated circuits; frequency dividers; gallium arsenide; high electron mobility transistors; integrated logic circuits; 0.2 micron; 18 to 34 GHz; AlGaAs-GaAs-AlGaAs; AlGaAs/GaAs/AlGaAs quantum-well transistors; HEMT network model; SBFL inverter; SPICE simulation; data storage; dynamic frequency divider; high electron mobility transistor; memory type flip-flop; ring oscillators; source followers; transfer gates; Clocks; Electrical resistance measurement; Flip-flops; Frequency conversion; Frequency measurement; HEMTs; Inverters; Low voltage; Memory; Ring oscillators;
Conference_Titel :
Solid-State Circuits Conference, 1993. Digest of Technical Papers. 40th ISSCC., 1993 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0987-1
DOI :
10.1109/ISSCC.1993.280008
