Hypnos: An ultra-low power sleep mode with SRAM data retention for embedded microcontrollers!

In heavily duty-cycled embedded systems, the energy consumed by the microcontroller in idle mode is often the bottleneck for battery lifetime. Existing solutions address this problem by placing the microcontroller in a low power (sleep) state when idle, and preserving application state either by retaining the data in-situ in SRAM, or by checkpointing it to FLASH. However, both these approaches have notable drawbacks. In-situ data retention requires the SRAM to remain powered in sleep mode, while checkpointing to FLASH involves significant energy and time overheads. This paper proposes a new ultra-low power sleep mode for micro-controllers that overcomes the limitations of both these ap- proaches. Our technique, HYPNOS, is based on the key observation that the on-chip SRAM in a microcontroller exhibits 100% data retention even at a much lower supply voltage (as much as 10x lower) than the typical operating voltage of the microcontroller. HYPNOS exploits this observation by performing extreme voltage scaling when the microcontroller is in sleep mode. We implement and evaluate HYPNOS for the TI MSP430G2452 microcontroller and show that the MCU draws only 26nA in the proposed sleep mode, which is 4× lower than any existing sleep mode that preserves SRAM contents. Further, we show that a complete wireless sensing system using HYPNOS only depletes battery capacity by 42.6nAh in an hour. By decreasing the average power consumption to such minuscule levels, HYPNOS takes a significant step forward in making perpetual systems a reality through the use of energy harvesting.