5 V-to-75 V CMOS output interface circuits

Author

Declerq, M.J. ; Schubert, M. ; Clement, F.

Author_Institution

ETH, Lausanne, Switzerland

fYear

1993

Firstpage

162

Lastpage

163

Abstract

A family of CMOS low- to high-voltage output interface circuits based on a standard, unmodified low-voltage CMOS technology is described. Using only thin-oxide high-voltage (HV) devices with reduced V/sub GS/ (gate-to-source voltage) swing, it makes use of level-shift techniques to meet the constraints on the gate control signals. These static circuits permit the full output voltage swing of V/sub DDH/, while keeping the V/sub GS/ swing of the output devices within the safety limits, including during HV supply transients. Using a standard 2- mu m n-well CMOS technology, reliable, reproducible V/sub DS/ breakdown voltages as high as 120 V and 80 V have been obtained for HV-nMOS and HV-pMOS devices, respectively.<>

Keywords

CMOS integrated circuits; convertors; digital integrated circuits; linear integrated circuits; power integrated circuits; 120 V; 2 micron; 5 V; 75 V; 80 V; HV-nMOS; HV-pMOS; LV/HV interface circuits; analogue interface; digital interface; level-shift techniques; low-voltage CMOS technology; n-well CMOS technology; output interface circuits; static circuits; thin oxide HV devices; Active matrix technology; Breakdown voltage; CMOS logic circuits; CMOS technology; Costs; Driver circuits; Mirrors; Parasitic capacitance; Safety devices; Standards publication;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1993. Digest of Technical Papers. 40th ISSCC., 1993 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-0987-1

Type

conf

DOI

10.1109/ISSCC.1993.280014

Filename

280014