Hardware Design of Quasi-Cyclic Low-Density Parity-Check Encoder Based on a Novel RC-Scheme

In this paper, quasi-cyclic low-density parity-check (QC- LDPC) codes are applied to a novel rate-compatible (RC) scheme for multimedia transmission. To ensure that the RC codes over the entire range of rates can be decoded by a single decoder, modified array codes in a lower triangular form are employed as the mother codes. The constructed rate-compatible QC-LDPC codes based on our novel RC- scheme can also be encoded by a single encoder. Hardware design of QC-LDPC encoder for this RC-scheme is proposed in detail. The hardware complexity is determined by the lowest-rate code for serial encoding and by the mother code for parallel encoding. Part of hardware units is disabled in certain cases to reduce power consumption.