Design of 32-bit TX2 microprocessor based on TRON specifications

Author

Goto, Harutaka ; Otaguro, Yukio ; Utsumi, Toru ; Masuda, Eiji ; Nozuyama, Yasuyuki ; Mitaya, M.

Author_Institution

Toshiba Corp., Saiwai-ku, Kawasaki, Japan

fYear

1993

Firstpage

68

Lastpage

77

Abstract

The TX2 processor is the second implementation in the Toshiba TLCS90000/TX series of 32-b microprocessors based on the TRON specification. The TX2 micro-architecture defines five functional units which implement a four-stage pipeline. Basic instructions with register-register operation are executed in a single cycle with a single step of microcode. The TX2 has a performance of 25 MIPS and executes about 20,000 dhrystones/second at 25 MHz with zero wait external bus cycle. Design of the TX2 is based on full custom LSI design methodology. To increase the operating frequency of the CISC microprocessor TX2, timing design based on static path delay analysis was performed. As a result, high speed processing has been achieved

Keywords

distributed processing; microprocessor chips; performance evaluation; real-time systems; 25 MHz; 25 MIPS; 32 bit; TRON computerised environment; TRON specification; TX2 micro-architecture; Toshiba TLCS90000/TX series; four-stage pipeline; full custom LSI design methodology; functional units; register-register operation; static path delay analysis; zero wait external bus cycle; Application specific integrated circuits; Clocks; Delay; Design methodology; Frequency; Microprocessors; Switches; Systems engineering and theory; Testing; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

TRON Project International Symposium. 1993., The 10th

Conference_Location

Tokyo

ISSN

1063-6749

Print_ISBN

0-8186-4580-6

Type

conf

DOI

10.1109/TRON.1993.589173

Filename

589173