• DocumentCode
    1696959
  • Title

    Sea of leads ultra high-density compliant wafer-level packaging technology

  • Author

    Bakir, Muhannad S. ; Reed, Hollie A. ; Kohl, Paul A. ; Martin, Kevin P. ; Meindl, James D.

  • Author_Institution
    Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
  • fYear
    2002
  • fDate
    6/24/1905 12:00:00 AM
  • Firstpage
    1087
  • Lastpage
    1094
  • Abstract
    Sea of leads (SoL) is a novel ultra high-density compliant wafer-level packaging technology. SoL extends wafer-level batch processing of multilayer on-chip interconnect networks to include x-y-z compliant chip input/output (I/O) interconnects with a density exceeding 104 leads per cm2. A package with 12×103 compliant leads distributed across a cm2 has been demonstrated. The compliance enables wafer-level testing as well as eliminates the need for underfill between chips and substrates with a CTE (coefficient of thermal expansion) mismatch thereby enhancing reliability, electrical performance, manufacturing throughput, and cost. Two methods of fabricating nonadherent or ´slippery´ leads are demonstrated. The fabrication of slippery leads is desirable because adhesion between the lead and the package polymer layer is eliminated thereby freeing the leads to stretch and contract during thermal cycling. Compared to adherent leads, preliminary results show that slippery leads enhance the overall in-plane compliance. Moreover, the feasible z-axis compliance attained from polymer films with and without embedded air-gaps is compared.
  • Keywords
    adhesion; integrated circuit interconnections; integrated circuit packaging; integrated circuit reliability; integrated circuit testing; polymer films; thermal expansion; CTE mismatch; SoL; adhesion; cost; embedded air-gaps; manufacturing throughput; multilayer on-chip interconnect networks; package polymer layer; polymer films; reliability; sea of leads packaging technology; slippery leads; thermal cycling; ultra high-density compliant wafer-level packaging; wafer-level batch processing; wafer-level testing; z-axis compliance; Costs; Fabrication; Manufacturing; Network-on-a-chip; Nonhomogeneous media; Packaging; Testing; Thermal expansion; Throughput; Wafer scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference, 2002. Proceedings. 52nd
  • ISSN
    0569-5503
  • Print_ISBN
    0-7803-7430-4
  • Type

    conf

  • DOI
    10.1109/ECTC.2002.1008237
  • Filename
    1008237