Title :
Si bipolar multiplexer, demultiplexer, and prescaler ICs for 10 Gb/s SONET systems
Author :
Harada, T. ; Yoshihara, K. ; Masuzawa, K. ; Kagami, J. ; Nagai, K. ; Ikeda, T. ; Shiba, T. ; Kawasaki, K.
Author_Institution :
Hitachi Ltd., Tokyo, Japan
Abstract :
Silicon bipolar 4:1 multiplexer and 1:4 demultiplexer ICs with retiming functions, and a 1/64 prescaler IC with a comparator for a phase lock loop are reported. All clock dividers are static so that the ICs operate at any data rate from DC to over 10 Gb/s. The output data of the multiplexer and the input data of the demultiplexer are retimed by the data-rate clock at a flip-flop that minimizes multiplexer output pattern jitter and enlarges demultiplexer input phase margin. The ICs use a Si bipolar process featuring U-groove isolated double poly-silicon transistors on a SOI substrate, highly accurate poly-silicon resistors, MOS capacitors, and three levels of metal interconnects, including surface gold metal for packaging. Packaged ICs operate above 10.5 Gb/s, 12.0 Gb/s, and 16.0 GHz for the multiplexer, demultiplexer, and prescaler, respectively.<>
Keywords :
SONET; bipolar integrated circuits; demultiplexing equipment; digital communication systems; digital integrated circuits; elemental semiconductors; multiplexing equipment; optical communication equipment; scaling circuits; silicon; 10 Gbit/s; 16 GHz; MOS capacitors; SOI substrate; Si bipolar process; U-groove isolated; clock dividers; comparator; demultiplexer; double poly-silicon transistors; monolithic ICs; multiplexer; phase lock loop; prescaler; retiming functions; Bipolar integrated circuits; Clocks; Flip-flops; Jitter; MOS capacitors; MOSFETs; Multiplexing; Packaging; Resistors; Silicon;
Conference_Titel :
Solid-State Circuits Conference, 1993. Digest of Technical Papers. 40th ISSCC., 1993 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0987-1
DOI :
10.1109/ISSCC.1993.280018
