DocumentCode
1697040
Title
Board level reliability testing for power semiconductors in extended use applications
Author
Lang, Dennis
Author_Institution
Fairchild Semicond., San Jose, CA
fYear
2006
Abstract
The creation of the IPC-9701 standard for the board level testing of electronic component packages is filling the need for a standardized test for mechanical failures that portend electrical failures. Of course, with this new standard, there are new challenges. There are fundamental package design features that for many types of power device do not allow daisy chain testing as required by the IPC-9701 specification. Working with a customer Fairchild has modified the IPC test to accommodate the specific needs of discrete MOSFETs, and better simulate the use conditions than the IPC spec would. Finite element modeling of the assembly tested to the IPC-9701 specification, as well as the new proposal will be provided to compare the stresses induced by each method. Test data to the proposed conditions and the subsequent results for a specific power discrete device will be presented. Void criteria will also be explored based on devices mounted with voiding then tested
Keywords
finite element analysis; power semiconductor devices; semiconductor device packaging; semiconductor device reliability; standards; Finite element modeling; IPC-9701 standard; board level reliability testing; daisy chain testing; package design; power semiconductor; Assembly; Electronic components; Electronic equipment testing; Electronics packaging; Filling; Finite element methods; MOSFETs; Semiconductor device packaging; Semiconductor device reliability; Semiconductor device testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Applied Power Electronics Conference and Exposition, 2006. APEC '06. Twenty-First Annual IEEE
Conference_Location
Dallas, TX
Print_ISBN
0-7803-9547-6
Type
conf
DOI
10.1109/APEC.2006.1620644
Filename
1620644
Link To Document