Design of high frequency phase locked loop

Author

Bondare, Raman ; Dethe, C.G. ; Bhoyar, D.B. ; Mushrif, M.M.

Author_Institution

S.V.S.S. Coll. of Eng. & Res., India

fYear

2010

Firstpage

586

Lastpage

591

Abstract

A digital phase-locked loop (DPLL) is designed using 0.18 mm CMOS process and a 3.3 V power supply. It operates in the frequency range 200 MHz-1 GHz. The DPLL operation includes two stages: (i) a novel coarse-tuning stage based on a flash algorithm, and (ii) a fine-tuning stage similar to conventional DPLLs. The flash portion of the DPLL is made up of frequency comparators, an encoder and a decoder which drives a multiple charge pump (CP)/low pass filter (LPF) combination. Design considerations of the flash DPLL circuit components as well as implementation using Tanner design tools are presented. Spectra simulations were also performed and demonstrated a significant improvement in the lock time of the flash DPLL as compared to the conventional DPLL.

Keywords

CMOS digital integrated circuits; charge pump circuits; circuit simulation; circuit tuning; comparators (circuits); digital phase locked loops; low-pass filters; CMOS process; LPF; Tanner design tool; coarse-tuning; decoder; digital phase-locked loop; encoder; fine-tuning; flash DPLL circuit; flash algorithm; frequency 200 MHz to 1 GHz; frequency comparator; high frequency phase locked loop design; low pass filter; multiple charge pump; size 0.18 mm; spectra simulation; voltage 3.3 V; Arrays; Decoding; Phase frequency detector; Phase locked loops; Time frequency analysis; Voltage control; Voltage-controlled oscillators; CP; FC; LPF; MCP; PFD; VCO;

fLanguage

English

Publisher

ieee

Conference_Titel

Communication Control and Computing Technologies (ICCCCT), 2010 IEEE International Conference on

Conference_Location

Ramanathapuram

Print_ISBN

978-1-4244-7769-2

Type

conf

DOI

10.1109/ICCCCT.2010.5670772

Filename

5670772