DocumentCode
1697082
Title
Prime Indicants: A Synthesis Method for Indicating Combinational Logic Blocks
Author
Toms, W.B. ; Edwards, D.A.
Author_Institution
Sch. of Comput. Sci., Univ. of Manchester, Manchester
fYear
2009
Firstpage
139
Lastpage
150
Abstract
Self-timed circuits present an attractive solution to the problem of process variation. However, implementing self-timed combinational logic is complex and expensive. This paper presents a novel method for synthesising indicating implementations of arbitrary encoded function blocks. The synthesis method reduces the cost of the implementations by distributing indication between the individual outputs of a function block. Covers are constructed by determining the minimal cost set of Prime Indicants which are required to indicate all of the input transitions of the function block. The results of the procedure are demonstrated on a wide range of combinational logic blocks and show a reduction in literal count of between 38-99%.
Keywords
combinational circuits; network synthesis; arbitrary encoded function blocks; combinational logic blocks; literal count; prime indicants; self-timed circuits; Asynchronous circuits; Circuit synthesis; Circuit testing; Combinational circuits; Computer science; Cost function; Logic; Network synthesis; Timing; Very large scale integration; Quasi-Delay Insensitive Speed Independent; Self-Timed Combinational Logic Synthesis;
fLanguage
English
Publisher
ieee
Conference_Titel
Asynchronous Circuits and Systems, 2009. ASYNC '09. 15th IEEE Symposium on
Conference_Location
Chapel Hill, NC
ISSN
1522-8681
Print_ISBN
978-1-4244-3933-1
Type
conf
DOI
10.1109/ASYNC.2009.24
Filename
5010344
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