A 9 ns 16 Mb CMOS SRAM with offset reduced current sense amplifier

Author

Seno, K. ; Knorpp, K. ; Shu, L.-L. ; Miyaji, F. ; Sasaki, M. ; Takeda, M. ; Yokoyama, T. ; Fujita, K. ; Kimura, T. ; Tomo, Y. ; Chuang, P. ; Kobayashi, K.

Author_Institution

Sony Corp., Kanagawa, Japan

fYear

1993

Firstpage

248

Lastpage

249

Abstract

A 4-Mb*4 SRAM (static random access memory) with a 9-ns access time that uses a 0.35- mu m CMOS process with KrF excimer laser lithography is descibed. The 9-ns access time is achieved by using a current-mode nonequalized read data path with an offset-reduced stabilized-feedback current sense amplifier and a quadrant-organization architecture. The design includes a current-mode wired-OR 64-b*4 parallel test circuit. The typical address access time is 9 ns at a supply voltage of 3.3 V and an output load capacitance of 30 pF. Active current is 72 mA at 30 MHz under typical conditions.<>

Keywords

CMOS integrated circuits; SRAM chips; built-in self test; integrated circuit testing; 0.35 micron; 0.35- mu m CMOS; 16 Mbit; 3.3 V; 30 MHz; 30 pF; 72 mA; 9 ns; BIST; CMOS SRAM; KrF excimer laser lithography; current-mode nonequalized read data path; offset reduced current sense amplifier; parallel test circuit; quadrant-organization architecture; stabilized-feedback; static random access memory; CMOS process; Circuit testing; Clocks; MOS devices; Microelectronics; Operational amplifiers; Optical design; Power amplifiers; Random access memory; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1993. Digest of Technical Papers. 40th ISSCC., 1993 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-0987-1

Type

conf

DOI

10.1109/ISSCC.1993.280028

Filename

280028