A 1.5 ns 256 kb BiCMOS SRAM with 11 k 60 ps logic gates

Author

Tamba, N. ; Akimoto, K. ; Ohhayashi, M. ; Hiramoto, T. ; Kokubu, T. ; Ohmori, S. ; Muraya, T. ; Kishimoto, A. ; Tsuji, S. ; Hayashi, H. ; Handa, H. ; Igarashi, T. ; Fujiwara, T. ; Watanabe, K. ; Uchida, A. ; Odaka, M. ; Nambu, H. ; Yamaguchi, K. ; Ikeda,

Author_Institution

Hitachi Ltd., Tokyo, Japan

fYear

1993

Firstpage

246

Lastpage

247

Abstract

The authors present a chip with 1.5-ns access SRAM (static random access memory) and 60-ps logic gates that uses a BiCMOS memory technology with ECL (emitter coupled logic)-CMOS circuits and a 0.5- mu m BiCMOS process providing double-polysilicon bipolar transistors. The chip consists of a gate array and two RAM blocks. The RAM block has four RAM macros, a custom logic macro and a write-pulse generator. A RAM macro contains two 1-kW*32-b arrays with bit redundancy and peripheral circuits. Input/output circuits are at the chip periphery. The RAM operates over a wide range of the supply voltage. Measured output-latch path delay is 2.4 ns at VEE=-4 V. RAM access time is 1.5 ns. Write pulse width is 1.3 ns.<>

Keywords

BiCMOS integrated circuits; SRAM chips; emitter-coupled logic; logic arrays; logic gates; redundancy; 0.5 micron; 1.3 ns; 1.5 ns; 256 kbit; 60 ps; BiCMOS SRAM; ECL; RAM blocks; bit redundancy; custom logic macro; double-polysilicon bipolar transistors; emitter coupled logic; gate array; logic gates; peripheral circuits; static random access memory; write-pulse generator; BiCMOS integrated circuits; Bipolar transistors; Coupling circuits; Logic circuits; Logic gates; Random access memory; Read-write memory; SRAM chips; Semiconductor device measurement; Voltage measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1993. Digest of Technical Papers. 40th ISSCC., 1993 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-0987-1

Type

conf

DOI

10.1109/ISSCC.1993.280029

Filename

280029