A low-power generator-based FIFO using ring pointers and current-mode sensing

The authors present a submicron full CMOS FIFO (first in, first out) memory generator for ASIC (application-specific integrated circuit) and full-custom applications that combines asynchronous access, shift register pointers, a direct word line comparison technique (DWLC) for flag generation, and current sensing in a regular structured architecture that uses circuit compaction and automated parameteric characterization. It features overread and write protection and retransmit capability at clock rates of 70-100 MHz at 5 V and 40-60 MHz at 3.3 V. The regular structure yields predictable performance and simplifies timing model synthesis for simulators. Special hardware features support full fault coverage with BIST (built-in self-test) algorithms available in hardware or software.<>