Yield prediction using calibrated critical area modelling

This paper describes how critical area software can be used in the accurate prediction of the yield of ASIC designs. The approach is based on calculating the actual area of the design most sensitive to defects, rather than using the traditional methods of using die area to calculate the yield. An obstacle course test structure is used to calibrate the software tools, by extracting values for inter and intra layer defect densities. The tools are then used to predict yield improvements on designs which have been modified to improve process yield