Title :
Neuron MOS winner-take-all circuit and its application to associative memory
Author :
Yamashita, T. ; Shibata, T. ; Ohmi, T.
Author_Institution :
Tohoku Univ., Sandai, Japan
Abstract :
An implementation of a winner-take-all circuit that is based on a neuron MOSFET, a transistor that simulates the function of biological neurons with a single device, is presented. A standard double-polysilicon CMOS process is used to implement an associative memory network in which the stored data set closest to the input data is selected. Even if the data stored in the associative memory do not exactly match the sample data, the circuit finds the closest data set using a vMOS winner-take-all circuit. The winner-take-all circuit containing two unit cells is shown. Experimental results demonstrating how the circuit determines the ´winner´ and ´loser´ are presented. Simulation results for the sorting circuit are also presented.<>
Keywords :
CMOS integrated circuits; content-addressable storage; neural chips; MOS winner-take-all circuit; Si; associative memory; double-polysilicon CMOS process; neuron MOSFET; Associative memory; Coupling circuits; Feedback circuits; Feedback loop; Inverters; MOSFETs; Neurofeedback; Neurons; Nonvolatile memory; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 1993. Digest of Technical Papers. 40th ISSCC., 1993 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0987-1
DOI :
10.1109/ISSCC.1993.280034
