Low power FIR filter realization with differential coefficients and input

Most FIR filter realizations use the inputs and coefficients directly to compute the convolution. We present a low power and high speed FIR filter designs by using first order difference between inputs and various orders of differences between coefficients. This design first reformulates the FIR operations with the differences in the algorithm level. Then, in the architecture level, we adopt the distributed arithmetic (DA) architecture to exploit the probability distribution such that the power consumption can be reduced further. The design is applied to an example FIR filter to quantify the energy savings and speedup. It shows lower power consumption than the previous design with the comparable performance