• DocumentCode
    1697500
  • Title

    B-algorithm: a behavioral test generation algorithm

  • Author

    Cho, Chang Hyun ; Armstrong, James R.

  • Author_Institution
    Micro Device Bus., Samsung Electron. Co., Bunchun, South Korea
  • fYear
    34608
  • Firstpage
    968
  • Lastpage
    979
  • Abstract
    A behavioral test generation algorithm (called the B-algorithm) is presented which generates tests directly from behavioral VHDL circuit descriptions using three types of behavioral faults (behavioral stuck-at faults, behavioral stuck-open faults, and micro-operation faults). Behavioral faults are defined by perturbing VHDL constructs. In particular, behavioral stuck-at faults are defined for virtual signals corresponding to expressions as well as for normal signals. The B-algorithm generates tests using three basic test generation operations (activation, propagation, and justification), which are systematically executed by manipulating three data structures (B-frontier, J-frontier, and A-queue). Rules for the test generation operations are defined using the concepts of two-phase activation and two-phase propagation. The B-algorithm has two unique features. First, it can generate tests for behavioral stuck-open faults, which in fact can detect some gate level transition faults. Second, it incorporates the concept of two-phase testing, a testing strategy where a fault is detected using two consecutive test sequences
  • Keywords
    VLSI; fault location; hardware description languages; integrated logic circuits; logic CAD; logic testing; A-queue; B-algorithm; B-frontier; J-frontier; activation; behavioral VHDL circuit descriptions; behavioral faults; behavioral test generation algorithm; gate level transition fault; justification; micro-operation faults; perturbing VHDL constructs; propagation; stuck-at faults; stuck-open faults; three data structures; two-phase activation; two-phase propagation; virtual signals; Circuit faults; Circuit testing; Electrical fault detection; Electronic equipment testing; Fault detection; Logic testing; Microprocessors; Switches; System testing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 1994. Proceedings., International
  • Conference_Location
    Washington, DC
  • ISSN
    1089-3539
  • Print_ISBN
    0-7803-2103-0
  • Type

    conf

  • DOI
    10.1109/TEST.1994.528046
  • Filename
    528046