An adaptive equalizing maximum likelihood decoding LSI for magnetic recording systems

Author

Tanaka, S. ; Kojima, H. ; Okada, Y. ; Nakazawa, F. ; Hikage, T. ; Matsushige, H. ; Kosuge, M. ; Miyasaka, H. ; Takashi, T. ; Hanamura, S.

Author_Institution

Hitachi Ltd., Tokyo, Japan

fYear

1993

Firstpage

220

Lastpage

221

Abstract

Describes a fully digital microprogrammable signal processor chip for magnetic tape (MT) recording systems which contains an adaptive equalizer, a maximum-likelihood decoder for various codes, a clock-recovery circuit, and an analog-phase-locked loop (PLL). Microprogrammable signal-processing cores reduce the number of gates by 40% compared to conventional design and provide flexibility for various recording codes. The micrograph of the fabricated LSI is shown. The process is in 1.0- mu m CMOS. Performance is summarized, and the analog input and equalized wave forms are presented.<>

Keywords

CMOS integrated circuits; decoding; digital signal processing chips; equalisers; large scale integration; magnetic recording; maximum likelihood estimation; 1.0 micron; CMOS; adaptive equalizer; analog-phase-locked loop; clock-recovery circuit; equalized wave forms; magnetic recording systems; magnetic tape recording; maximum likelihood decoding; micrograph; microprogrammable signal processor chip; recording codes; Adaptive equalizers; Clocks; Digital magnetic recording; Large scale integration; Magnetic circuits; Magnetic cores; Maximum likelihood decoding; Phase locked loops; Signal design; Signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1993. Digest of Technical Papers. 40th ISSCC., 1993 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-0987-1

Type

conf

DOI

10.1109/ISSCC.1993.280040

Filename

280040