A discrete-time analog signal processor for disk read channels

Author

Gomez, R. ; Rofougaran, M. ; Abidi, A.A.

Author_Institution

California Univ., Los Angeles, CA, USA

fYear

1993

Firstpage

212

Lastpage

213

Abstract

A signal processor that incorporates equalization, clock recovery, AGC (automatic gain control), and peak detection for waveforms in the disk read channel and operates up to a 40-MHz clock rate is described. The 2- mu m CMOS IC uses precision analog MOS signal processing implemented with scaled-down unit cells and dissipates 500 mW from a 5-V power supply. The IC layout is hand-crafted. The 6.8-mm*4.6-mm die is fabricated in a 2- mu m, double-poly, double-metal technology. Measurements on one half-delay cell show a transfer efficiency of 0.994 and 10-b linearity across full-scale.<>

Keywords

CMOS integrated circuits; analogue processing circuits; automatic gain control; equalisers; magnetic disc storage; 2 micron; 5 V; 500 mW; AGC; CMOS IC; IC layout; clock recovery; discrete-time analog signal processor; disk read channels; double-metal technology; double-poly technology; equalization; half-delay cell; linearity; peak detection; precision analog MOS signal processing; scaled-down unit cells; transfer efficiency; Analog integrated circuits; CMOS analog integrated circuits; CMOS integrated circuits; CMOS process; CMOS technology; Clocks; Gain control; Integrated circuit layout; Power supplies; Signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1993. Digest of Technical Papers. 40th ISSCC., 1993 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-0987-1

Type

conf

DOI

10.1109/ISSCC.1993.280044

Filename

280044