Title :
Optimization of Current-Mode MVD-ORNS Arithmetic Circuits
Author :
Inaba, Motoi ; Tanno, Koichi ; Sawada, Ryota ; Tanaka, Hisashi ; Tamura, Hiroki
Author_Institution :
Fac. of Ind. Technol., Tsukuba Univ. of Technol., Tsukuba
Abstract :
In this paper, optimization and verification of the current-mode fundamental arithmetic circuits employing MVD-ORNS are presented. MVD-ORNS is the redundant number system using logic levels in the multiple-valued logic. In order to get over weak points of ordinary circuits, the algorithms and circuit components for addition, subtraction and multiplication are reconsidered through the logical analysis and HSPICE simulation with CMOS 0.35 micrometer device parameters. As results in the 4-bit multiplier, the maximum logic level and the number of modulo operations in the series connection are successfully reduced to 29 from 49 and to 2 from 3, respectively. HSPICE simulation also shows the good results, for example the proposed switched current mirrors are very effective to bring both of the stable operation and low power dissipation to the current-mode arithmetic circuits. The proposed MVD-ORNS circuits are expected to realize the high-speed full-parallel calculation without any carry/borrow propagation.
Keywords :
SPICE; digital arithmetic; logic circuits; CMOS 0.35 micrometer device parameters; HSPICE simulation; current-mode MVD-ORNS arithmetic circuits; logic levels; maximum logic level; multiple-valued logic; Algorithm design and analysis; Analytical models; Arithmetic; CMOS logic circuits; Circuit simulation; Logic devices; Mirrors; Power dissipation; Signal processing algorithms; Switching circuits; Current-mode CMOS arithmetic circuit; Multiple-valued logic; ORNS;
Conference_Titel :
Multiple-Valued Logic, 2009. ISMVL '09. 39th International Symposium on
Conference_Location :
Naha, Okinawa
Print_ISBN :
978-1-4244-3841-9
Electronic_ISBN :
0195-623X
DOI :
10.1109/ISMVL.2009.48