Low-power reconfigurable signal processing via dynamic algorithm transformations (DAT)

Presented in this paper are dynamic algorithm transformations (DAT) for systematic design of reconfigurable computing engines. These techniques allow dynamic alteration of algorithm properties in response to input non-stationarities. The input is modeled as a set of states with an underlying probability distribution, 𝒫_S. For each input state s, a signal monitoring algorithm (SMA) computes a power-optimal configuration for the signal processing algorithm (SPA) block. A fraction α of the (SPA) block is hardwired and the remaining (1-α) is reconfigurable. Similarly, the (SMA) block computation is partitioned into a fraction β for the memory and the remaining (1-β) for the data path. For the given input state distribution, the optimal values of α (α_opt) and β (β_opt) are determined. It is shown that for frequency selective filtering (FIR filters), the power savings of 35%-45% can be achieved by a DAT-based reconfigurable system as compared to the traditional design based on the worst-case scenario