A counter-based SR forward converter with standby power reduction considered

In this paper, a field programmable gate arrays (FPGA) technique applied to a forward converter with synchronous rectification (SR) is utilized to design a pulse-width-modulation (PWM) proportional-integral-derivative (PID) controller, along with protection peripherals. With only one comparator and without any analog-to-digital converter (ADC), the information on the feedback output voltage is entirely obtained according to a counter. In the continuous current mode (CCM), the next duty cycle is determined by the present duty cycle, and in the discontinuous current mode (DCM) used to reduce power dissipated at light load, the next duty cycle is also decided by the present duty cycle but with some modifications which reduce the effect of variations on the calculated duty cycle. In this paper, the detailed operation of this control topology is illustrated, along with some experimental results to verify its effectiveness.