A RISC architecture with uncompromised digital signal processing and microcontroller operation

Digital signal processors are paired with microcontrollers in many applications. Various attempts have been made to combine the two processor functions in one architecture, but there have remained two unresolved conflicts. These are different data and program memory hierarchy choices in speed and size, and different real-time control needs. This paper reviews the basic processing requirements for digital signal processing (DSP) and controllers and shows how a new 32-bit RISC architecture has resolved these conflicts and successfully integrated the two functions seamlessly into one processor core. This is confirmed with a detailed FIR filter example. Major innovations in this tricore architecture are a novel memory organization used along with variable instruction word sizes and multiple issuing of instructions