Title :
A CPL-based dual supply 32-bit ALU for sub 180 nm CMOS technologies
Author :
Chatterjee, Bhaskar ; Sachdev, Manoj ; Krishnamurthy, Ram
Author_Institution :
Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
Abstract :
In this paper we present the design of a high performance 32-bit ALU for low power applications. We use dual power supply scheme and CPL logic for non-critical units of the ALU. In addition, latches with only n-MOS clocked transistors are used to interface logic operating at different power supplies and achieve static power free operation. Our simulation results indicate that, for the 180 nm-65 nm CMOS technologies it is possible to reduce the ALU total energy by 18%-24%, with minimal delay degradation. In addition, there is up to 22%-32% reduction in leakage power in the standby mode.
Keywords :
CMOS integrated circuits; circuit simulation; delays; digital arithmetic; integrated circuit design; leakage currents; logic design; low-power electronics; microprocessor chips; power supply circuits; 180 to 65 nm; 32 bit; ALU design; ALU total energy; CMOS technologies; CPL logic; CPL-based dual supply ALU; delay degradation; dual power supply scheme; leakage power reduction; logic interface; low power applications; n-MOS clocked transistor latches; noncritical units; operating power supplies; simulation; standby mode; static power-free operation; CMOS logic circuits; CMOS technology; Clocks; Degradation; Delay; Frequency; Integrated circuit technology; Microprocessors; Power engineering and energy; Power engineering computing;
Conference_Titel :
Low Power Electronics and Design, 2004. ISLPED '04. Proceedings of the 2004 International Symposium on
Print_ISBN :
1-58113-929-2
DOI :
10.1109/LPE.2004.1349345
