Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation

Author

Schrom, Gerhard ; Hazucha, Peter ; Hahn, Jae-Hong ; Kursun, Volkan ; Gardner, Donald ; Narendra, Siva ; Karnik, Tanay ; De, Vivek

Author_Institution

Circuit Res., Intel Labs., Hillsboro, OR, USA

fYear

2004

Firstpage

263

Lastpage

268

Abstract

Rapidly increasing input current of microprocessors resulted in rising cost and motherboard real estate occupied by decoupling capacitors and power routing. We show by analysis that an on-die switching DC-DC converter is feasible for future microprocessor power delivery. The DC-DC converter can be fabricated in an existing CMOS process (90nm-180nm) with a back-end thin-film inductor module. We show that 85% efficiency and 10% output voltage droop can be achieved for 4:1, 3:1, and 2:1 conversion ratios, area overhead of 5% and no additional on-die decoupling capacitance. A 4:1 conversion results in 3.4× smaller input current and 6.8× smaller external decoupling.

Keywords

CMOS integrated circuits; DC-DC power convertors; computer power supplies; low-power electronics; microprocessor chips; power inductors; power supply circuits; switching convertors; 3D-stacked DC-DC converters; 85 percent; 90 to 180 nm; CMOS process; back-end thin-film inductor module; buck converter; cascode bridge; high-performance microprocessors; high-voltage switching; low-voltage process; microprocessor power delivery; monolithic DC-DC converters; on-die switching converter; peak supply current; smaller external decoupling; CMOS process; CMOS technology; Costs; DC-DC power converters; Microprocessors; Power capacitors; Routing; Switching converters; Thin film inductors; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, 2004. ISLPED '04. Proceedings of the 2004 International Symposium on

Print_ISBN

1-58113-929-2

Type

conf

DOI

10.1109/LPE.2004.1349348

Filename

1349348