A monolithic 480 Mb/s parallel AGC/decision/clock-recovery circuit in 1.2 mu m CMOS

Author

Hu, T.H. ; Gray, P.R.

Author_Institution

California Univ., Berkeley, CA, USA

fYear

1993

Firstpage

98

Lastpage

99

Abstract

An approach to AGC (automatic gain control), decision, and clock-recovery functions in data communications receivers in which technology speed limitations are overcome by using parallel signal paths in the receiver in a specified manner is described. The concept is demonstrated with experimental results from a 480-Mb/s AGC/decision/clock-recovery block implemented using 1.2- mu m doubly-poly CMOS technology. In this experimental circuit, the ratio of data rate to effective device f/sub T/ is only about 1 to 5. Extrapolated to 0.8- or 1- mu m CMOS, the technique has potential for implementing the AGC/decision/clock-recovery part of receivers with rates in the range of 600 to 800 Mb/s in standard single-poly digital CMOS technology.<>

Keywords

CMOS integrated circuits; automatic gain control; clocks; data communication equipment; digital integrated circuits; 0.8 to 1.0 micron; 1.2 micron; 480 Mbit/s; 600 to 800 Mbit/s; AGC; AGC/decision/clock-recovery block; clock-recovery functions; data communications receivers; doubly-poly CMOS technology; parallel signal paths; Bit rate; Circuits; Clocks; Filters; Frequency; Jitter; Parallel architectures; Phase locked loops; Ring oscillators; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1993. Digest of Technical Papers. 40th ISSCC., 1993 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-0987-1

Type

conf

DOI

10.1109/ISSCC.1993.280068

Filename

280068