The ChipCflow: A Tool to Generate Hardware Accelerators Using a Static Dataflow Machine Designed for a FPGA

Author

Fernandes Da Silva, Antonio Carlos ; Luiz e Silva, Jorge

Author_Institution

Coordination of Inf., Fed. Technol. Univ. of Parana, Cornelio Procopio, Brazil

fYear

2014

fDate

22-24 Oct. 2014

Firstpage

90

Lastpage

95

Abstract

The execution of sections of algorithms in hardware accelerators, appears as a alternative to speed up performance with low power consumption. In this article the Chip flow project is presented, the goal of Chip flow is conversion of C code in a static dataflow machine designed for a FPGA. The conversion process is discussed and some initial results are presented. The results of Chip flow are compared with a Intel core i7 processor and modern GPU. The results of benchmarks implemented show that Chip flow is a newer alternative for the development of hardware accelerators, with a good performance with low power consumption.

Keywords

C language; data flow computing; field programmable gate arrays; multiprocessing systems; power consumption; program compilers; C code conversion; ChipCflow; FPGA; Intel core i7 processor; chip flow project; compiler; conversion process; hardware accelerators; low power consumption; modern GPU; static dataflow machine; Computer architecture; Data buses; Field programmable gate arrays; Graphics processing units; Hardware; Power demand; Registers; Compiler; Dataflow; FPGA; Reconfigurable Computing;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Architecture and High Performance Computing Workshop (SBAC-PADW), 2014 International Symposium on

Conference_Location

Paris

Type

conf

DOI

10.1109/SBAC-PADW.2014.19

Filename

6972021