Title :
Electroplating Cu fillings for through-vias for three-dimensional chip stacking
Author :
Tomisaka, Manabu ; Yonemura, Hitoshi ; Hoshino, Masataka ; Takahashi, Kenji ; Okamura, Takuji ; Jun Sun, Jian ; Kondo, Kazuo
Author_Institution :
Electron. Syst. Integration Technol. Res. Dept., Assoc. of Super-Adv. Electron. Technol., Tsukuba, Japan
fDate :
6/24/1905 12:00:00 AM
Abstract :
Three-dimensional (3D) LSI chip stacking with through chip electrodes can realize high-density packaging and high-speed operation performance because the through chip electrode offers the shortest interconnection between stacked chips. The through chip via size we studied was 10 μm-square and 70 μm-deep. The void free plating is necessary to avoid problems caused by acid solutions remaining in voids. In this paper, systematic studies of the dependence of electroplating conditions on via filling are described. We found that vias could be almost filled completely.
Keywords :
copper; electroplating; integrated circuit interconnections; integrated circuit metallisation; integrated circuit packaging; large scale integration; multichip modules; voids (solid); 10 micron; 3D LSI chip stacking; 3D chip stacking; 70 micron; Cu; Cu through-via filling; acid solutions; electroplating; electroplating conditions; high-density packaging; high-speed operation; interconnection length; stacked chips; through chip electrodes; through chip via size; via filling; void free plating; Cathodes; Chemical technology; Electrodes; Etching; Filling; Integrated circuit interconnections; Large scale integration; Packaging; Printed circuits; Stacking;
Conference_Titel :
Electronic Components and Technology Conference, 2002. Proceedings. 52nd
Print_ISBN :
0-7803-7430-4
DOI :
10.1109/ECTC.2002.1008294
