3D interconnect through aligned wafer level bonding

Wafer level packaging and 3D interconnect technologies are driven by increasing device density and functionality as well as reduction of total packaging cost. Key enabling technologies for 3D interconnect are high precision alignment and bonding systems and thick resist processing. A unique processing equipment has been developed to meet high volume production requirements. This paper reviews advances in equipment processing capabilities and provides a guideline for new processing techniques available. Wafer to wafer alignment can be carried out in various ways. Traditionally aligned wafer bonding is a well-established technology in the MEMS industry. Special requirements for 3D interconnects are high accuracy, the use of single side processed wafers and 8 inch capability. A comparison of wafer alignment technologies is presented. Also, a novel face-to-face alignment method is described and analyzed in terms of alignment accuracy before and after bonding. Wafer bonding is carried out subsequent to the alignment step in a separate process module. A summary of different bonding methods is given. Intermediate layers that act as bonding agent can be spun on to the wafer. Such coating processes for wafer level packaging applications vary greatly from the requirements for VLSI processing. VLSI photoresist processes use thin layers to transfer small features with sub-micron tolerances. Wafer level bumping typically is performed with 5-150 μm films, to transfer large (20-250 μm) features, with tolerances approaching micron scale. HDI applications require thicker adhesive layers. The paper concludes with application examples with different intermediate layers such as BCB.