Design for testability in digitally-corrected ADCs

Author

Mangelsdorf, C. ; Lee, S.-H. ; Martin, M. ; Malik, H. ; Fukuda, T. ; Matsumoto, H.

Author_Institution

Analog Devices, Wilmington, MA, USA

fYear

1993

Firstpage

70

Lastpage

71

Abstract

A test methodology that reveals safety-margin problems is presented. The methodology allows diagnosis without additional hardware. To test the safety margin, the correction logic is inhibited. The coding of the first and second stages actually remains the same, but the first stage output is never decremented before the two stage outputs are combined to form the overall ADC (analog-to-digital converter) output code. This means that over a portion of the second-stage range, the ADC output code will be too high. An example of how a first-stage flash error is interpreted is shown. Here the safety margin is reduced by the shift of the first-stage transition. The technique described here has been demonstrated on a CMOS 10-b, 20-Ms/s ADC for camcorder applications.<>

Keywords

CMOS integrated circuits; analogue-digital conversion; coding errors; design for testability; error correction; integrated circuit testing; A/D convertor; CMOS; analog-to-digital converter; correction logic; digitally-corrected ADCs; safety-margin problems; test methodology; Design for testability; Error correction; Error correction codes; Hardware; Linearity; Logic testing; Pipelines; Quality assurance; Safety; Transfer functions;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1993. Digest of Technical Papers. 40th ISSCC., 1993 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-0987-1

Type

conf

DOI

10.1109/ISSCC.1993.280079

Filename

280079