Reliability study of 3-D stacked structures

Author

Heikkilä, Rami ; Tanskanen, Jarmo ; Ristolainen, Eero O.

Author_Institution

Tampere Univ. of Technol., Finland

fYear

2002

fDate

6/24/1905 12:00:00 AM

Firstpage

1449

Lastpage

1453

Abstract

The goal of this work is to introduce the manufacturing and testing of a 3D stacked structure. Dimensions of the system-in-package (SiP) solution of six chips were 14 mm×8 mm×0.8 mm. This module consists of three aramid-epoxy interposers, each containing two chips. The interposers were 150 μm thick and the chips were thinned down to 90 μm. The flip chip method was used to attach the chips to the interposers. Eutectic tin-lead solder bumps were used to mount the chips to the interposer. Tin-bismuth solder balls and solder-coated polymer spheres were used to stack the interposers on the top of each other. However, more attention was paid to testing different interconnection methods and materials.

Keywords

flip-chip devices; integrated circuit interconnections; integrated circuit packaging; microassembling; multichip modules; plastic packaging; soldering; 0.8 mm; 14 mm; 150 micron; 3D stacked structure manufacturing; 3D stacked structure testing; 8 mm; 90 micron; SnBi; SnPb; aramid-epoxy interposers; chip thinning; chip-interposer mounting; eutectic tin-lead solder bumps; flip chip attach; interconnection materials; interconnection methods; reliability; solder-coated polymer spheres; system-in-package; tin-bismuth solder balls; Bonding; Electronic packaging thermal management; Electronics packaging; Flip chip; Manufacturing; Packaging machines; Space technology; Stacking; Testing; Thermal stresses;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference, 2002. Proceedings. 52nd

ISSN

0569-5503

Print_ISBN

0-7803-7430-4

Type

conf

DOI

10.1109/ECTC.2002.1008297

Filename

1008297