Title :
A 10 b 100 Ms/s pipelined subranging BiCMOS ADC
Author :
Sone, K. ; Nakadai, N. ; Nishida, Y. ; Ishida, M. ; Sekine, Y. ; Yotsuyanagi, M.
Author_Institution :
NEC Corp., Kanagawa, Japan
Abstract :
The authors describe a 10-b, 100-Ms/s ADC (analog-to-digital converter) with a pipelined subranging scheme, a sample-and-hold amplifier with 7.6-ns acquisition time, and a 94-dB, 335-MHz op amp, enabling it to operate with 950-mW power dissipation from a single -5 V power supply. The design consists of sample-and-hold amplifiers, a coarse 6-b flash ADC, a fine 5-b flash ADC, a digital-to-analog converter, an analog subtractor, a register, and a digital adder with an error-correction function. The ADC is fabricated using a 0.8- mu m BiCMOS process featuring a double-layer polysilicon capacitor. The signal-to-noise-plus-distortion ratio as a function of input frequency at a 100-Ms/s conversion rate is shown.<>
Keywords :
BiCMOS integrated circuits; analogue-digital conversion; pipeline processing; -5 V; 0.8 micron; 10 bit type; 335 MHz; 7.6 ns; 94 dB; 950 mW; A/D convertor; BiCMOS ADC; double-layer polysilicon capacitor; error-correction function; flash ADC; op amp; pipelined subranging scheme; single -5 V power supply; Adders; Analog-digital conversion; BiCMOS integrated circuits; Capacitors; Digital-analog conversion; Frequency conversion; Operational amplifiers; Power amplifiers; Power dissipation; Power supplies;
Conference_Titel :
Solid-State Circuits Conference, 1993. Digest of Technical Papers. 40th ISSCC., 1993 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0987-1
DOI :
10.1109/ISSCC.1993.280081
