A 10 b 20 MHz 30 mW pipelined interpolating CMOS ADC

Author

Kusumoto, K. ; Murata, K. ; Matsuzawa, A. ; Tada, S. ; Maruyama, M. ; Oka, K. ; Konishi, H.

Author_Institution

Matsushita Electric Ind. Co. Ltd., Japan

fYear

1993

Firstpage

62

Lastpage

63

Abstract

A pipelined interpolating ADC which employs a chopper inverter amplifier capable of operating at low supply voltage is described. The DNL (differential nonlinearity) is less than +or-0.5 LSB at 20-MHz conversion frequency. The signal-to-noise and distortion ratio is 55 dB at 1 MHz for a 2 V pp analog input. The INL (integral nonlinearity) is less than +or-1.0 LSB. This ADC dissipates 30 mW with 2.5-V single supply at a 20-MHz conversion rate. The active area is 2.5 mm*2.6 mm in 0.8- mu m CMOS. The input capacitance is 12 pF.<>

Keywords

CMOS integrated circuits; analogue-digital conversion; pipeline processing; 0.8 micron; 10 bit type; 12 pF; 2.5 V; 20 MHz; 30 mW; 55 dB; A/D convertor; CMOS ADC; DNL; INL; chopper inverter amplifier; differential nonlinearity; integral nonlinearity; low supply voltage; pipelined interpolating ADC; Choppers; Circuit noise; Delay; Interpolation; Inverters; Noise reduction; Preamplifiers; Switched capacitor networks; Switches; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1993. Digest of Technical Papers. 40th ISSCC., 1993 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-0987-1

Type

conf

DOI

10.1109/ISSCC.1993.280083

Filename

280083