Title :
Reducing pipeline energy demands with local DVS and dynamic retiming
Author :
Lee, Seokwoo ; Das, Shidhartha ; Pham, Toan ; Austin, Todd ; Blaauw, David ; Mudge, Trevor
Author_Institution :
Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA
Abstract :
The quadratic relationship between voltage and energy has made dynamic voltage scaling (DVS) one of the most powerful techniques to reduce system power demands. Recently, techniques such as Razor DVS, voltage overscaling, and intelligent energy management have emerged as approaches to further reduce voltage by eliminating costly voltage margins inserted into traditional designs to ensure always-correct operation. The degree to which a global voltage controller can shave voltage margins is limited by imbalances in pipeline stage latency. Since all pipeline stages share the same voltage, the stage exercising the longest critical path will define the overall voltage of the system, even if other stages could potentially run at lower voltages. In this paper, we evaluate two local tuning mechanisms in the context of Razor DVS, a local voltage controller scheme that allows each pipeline stage its own voltage level, and a lower cost dynamic retiming scheme that incorporates per-stage clock delay elements to allow longer-latency pipeline stages to "borrow" time from shorter-latency stages. Using simulation, we draw two key insights from our study. First, mitigating pipeline stage imbalances render additional DVS energy savings. A Razor pipeline design with dynamic retiming finds an additional 12% energy savings over global voltage control (resulting in overall energy savings of more than 28% compared to fully-margined DVS). Second, we demonstrate that imbalances arise not only from design factors, but also from run-time characteristics. As the program (or program phase) changes, we see different logic paths in multiple stages exercised frequently, necessitating a dynamic fine-tuning of local control. This result suggests that even well-balanced pipelines could benefit from dynamic retiming.
Keywords :
circuit simulation; integrated circuit design; logic design; logic simulation; low-power electronics; pipeline processing; timing; DVS energy savings; Razor DVS; Razor pipeline design; always-correct operation; design factors; dynamic local control fine-tuning; dynamic retiming; dynamic voltage scaling; global voltage controller; intelligent energy management; local DVS; local tuning mechanisms; local voltage controller scheme; longer-latency pipeline stages; margined DVS; multiple stage logic paths; per-stage clock delay elements; pipeline energy demand reduction; pipeline stage imbalances; pipeline stage latency imbalances; pipeline stage voltage; pipeline stage voltage levels; program phase; run-time characteristics; shorter-latency stages; simulation; system power demands; voltage margins; voltage overscaling; Clocks; Costs; Delay effects; Dynamic voltage scaling; Energy management; Logic; Pipelines; Power demand; Runtime; Voltage control;
Conference_Titel :
Low Power Electronics and Design, 2004. ISLPED '04. Proceedings of the 2004 International Symposium on
Print_ISBN :
1-58113-929-2
DOI :
10.1109/LPE.2004.1349358