A 15 b 1 Ms/s digitally self-calibrated pipeline ADC

A digital calibration technique based on radix 1.93 that can be applied to pipeline or cyclic ADC (analog-to-digital converter) architectures is presented. An important advantage of this design is that calibration is performed in the digital domain, so that no extra analog circuitry, such as weighted capacitor arrays, and no extra clock cycles are needed. This calibration automatically accounts for capacitor mismatch, capacitor nonlinearity, charge injection, finite op-amp gain, and comparator offset. The fully differential pipeline ADC is implemented in an 11-V, 4 GHz, 2.4- mu m BiCMOS process.<>