Flash solid-state drive with 6 MB/s read/write channel and data compression

Author

Wells, S. ; Clay, D.

Author_Institution

Intel Corp., Folsom, CA, USA

fYear

1993

Firstpage

52

Lastpage

53

Abstract

A 42-MB 2.5-in drive that includes a thirty-Mb device flash array, an embedded processor, and an interface ASIC (application-specific integrated circuit) is described. The 0.7- mu m standard-cell ASIC contains drive interface circuitry, a 4-port buffer manager, a flash interface, and a Lempel-Ziv-type hardware compressor. The flash device architecture is optimized for cost-effective high-density systems. Overall system performance is compared to that of a typical 2.5-in drive. Drive read timing with parallel host, sector buffer, and flash transfer is shown.<>

Keywords

application specific integrated circuits; buffer storage; data compression; peripheral interfaces; semiconductor storage; storage management chips; 0.7 micron; 2.5 in; 32 MB; 4-port buffer manager; 6 MB/s; 8 Mbit; Lempel-Ziv-type hardware compressor; application-specific integrated circuit; data compression; drive interface circuitry; embedded processor; flash array; flash device architecture; flash interface; flash solid-state drive; high-density systems; interface ASIC; read/write channel; Application specific integrated circuits; Clocks; Costs; Data compression; Emulation; Energy consumption; Flash memory; Latches; Oscillators; Solid state circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1993. Digest of Technical Papers. 40th ISSCC., 1993 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-0987-1

Type

conf

DOI

10.1109/ISSCC.1993.280087

Filename

280087