A 30 ns 256 Mb DRAM with multi-divided array structure

Author

Sugibayashi, T. ; Takeshima, T. ; Naritake, I. ; Matano, T. ; Takada, H. ; Aimoto, Y. ; Furuta, K. ; Fujita, M. ; Saeki, T. ; Sugawara, H. ; Murotani, T. ; Kasai, N. ; Shibahara, K. ; Nakajima, K. ; Hada, H. ; Hamada, T. ; Aizaki, N. ; Kunio, T. ; Kakehas

Author_Institution

NEC Corp., Kanagawa, Japan

fYear

1993

Firstpage

50

Lastpage

51

Abstract

A 256-Mb DRAM (dynamic random-access memory) fabricated using 0.25- mu m CMOS technology is described. The DRAM has 16-b I/Os, 30-ns access time, and 35-mA operating current for 60-ns cycle time. Key circuits include a partial cell array activation scheme in a multidivided array structure with a dual word-line format for reducing power-line voltage bounce and operating current, a selective pull-up data-line architecture to increase I/O (input/output) width and to reduce current, and a time-sharing refresh to maintain a conventional refresh period without increasing power-line voltage bounce.<>

Keywords

CMOS integrated circuits; DRAM chips; 0.25 micron; 256 Mbit; 30 ns; 35 mA; 35-mA operating current; 60 ns; CMOS technology; DRAM; dual word-line format; dynamic RAM; dynamic random-access memory; multi-divided array structure; multidivided array; partial cell array activation scheme; selective pull-up data-line architecture; time-sharing refresh; Artificial intelligence; Decoding; Driver circuits; High power amplifiers; National electric code; Power supplies; Random access memory; Synthetic aperture sonar; Time sharing computer systems; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1993. Digest of Technical Papers. 40th ISSCC., 1993 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-0987-1

Type

conf

DOI

10.1109/ISSCC.1993.280088

Filename

280088