Title :
256 Mb DRAM technologies for file applications
Author :
Kitsukawa, G. ; Horiguchi, M. ; Kawaijiri, Y. ; Kawahara, T. ; Aikiba, T. ; Kawase, Y. ; Tachibana, T. ; Sakai, T. ; Aoki, M. ; Shukuri, S. ; Sagara, K. ; Nagai, R. ; Hasegawa, N. ; Yokoyama, N. ; Kisu, T. ; Yamashita, H. ; Kure, T. ; Nishida, T.
Author_Institution :
Hitachi Ltd., Tokyo, Japan
Abstract :
The authors describe 256-Mb DRAM (dynamic random access memory) technologies for file applications. A subthreshold-current limiting scheme for word drivers is shown. The scheme uses a pMOS switching transistor between the wordline voltage and the driver transistor common-source terminal. The subthreshold current of a 256-Mb DRAM is reduced to 3% by applying this scheme to word drivers and decoders, and the total data-retention current is less than that of a 64-Mb DRAM. A redundancy technique is shown which features subarray-by-subarray replacement instead of the conventional line-by-line replacement. To evaluate the circuit technologies described here, an experimental 256-Mb DRAM was fabricated using 0.25- mu m CMOS technology with phase-shift lithography. It uses a 0.72- mu m/sup 2/ RSTC cell with a storage capacitance of 25 fF and operates on a voltage of 1.5-3.6 V.<>
Keywords :
CMOS integrated circuits; DRAM chips; redundancy; 0.25 micron; 1.5 to 3.6 V; 25 fF; 256 Mbit; CMOS technology; DRAM technologies; RSTC cell; dynamic RAM; dynamic random access memory; file applications; pMOS switching transistor; phase-shift lithography; redundancy technique; subarray-by-subarray replacement; subthreshold-current limiting scheme; word drivers; Circuit faults; Data engineering; Decoding; Design engineering; Driver circuits; MOSFETs; Random access memory; Redundancy; Subthreshold current; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 1993. Digest of Technical Papers. 40th ISSCC., 1993 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0987-1
DOI :
10.1109/ISSCC.1993.280089
