Title :
An experimental DRAM with a NAND-structured cell
Author :
Hasegawa, T. ; Takashima, D. ; Ogiwara, R. ; Ohta, M. ; Shiratake, S.-i. ; Hamamoto, T. ; Yamada, T. ; Aoki, M. ; Ishibashi, S. ; Oowaki, Y. ; Watanabe, S. ; Masuoka, F.
Author_Institution :
Toshiba Corp., Kawasaki, Japan
Abstract :
A block-oriented DRAM (dynamic random-access memory) having a NAND-structured cell with 0.962- mu m/sup 2/ area using 0.4- mu m design rules is described. This DRAM realizes 32% chip-area reduction compared with a current DRAM. Block size is 512 B. Typical 112-ns block access and a 30-ns serial cycle are achieved. A time-division-multiplex sense-amplifier, a DRAM temporary storage cell, and an interleaved I/O register are used. The experimental 32-M*8-b DRAM chip is fabricated using 0.4- mu m twin-tub CMOS technology. Waveforms in the block-oriented access mode are shown. The process and performance are summarized.<>
Keywords :
CMOS integrated circuits; DRAM chips; 0.4 micron; 112 ns; 256 Mbit; 30 ns; NAND-structured cell; TDM sense amplifier; block-oriented DRAM; block-oriented access mode; chip-area reduction; dynamic RAM; dynamic random-access memory; interleaved I/O register; time-division-multiplex; twin-tub CMOS technology; Capacitance; Capacitors; Equivalent circuits; Flip-flops; Interference elimination; Power dissipation; Random access memory; Signal restoration; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 1993. Digest of Technical Papers. 40th ISSCC., 1993 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0987-1
DOI :
10.1109/ISSCC.1993.280090
