Title :
A 16 b low-power-consumption digital signal processor
Author :
Ueda, K. ; Sugimura, T. ; Okamoto, M. ; Marui, S. ; Ishikawa, T. ; Sakakihara, M.
Author_Institution :
Matsushita Electric Ind. Co. Ltd., Osaka, Japan
Abstract :
A 16-b digital signal processor (DSP) is described that realizes an 11.2-kb/s vector sum-excited linear predictive (VSELP) speech codec, chosen as the digital cellular standard in Japan. Power consumption of 70-mW at 3.5-V VDD is achieved by using a double-speed multiply-accumulate system, by improving logical and transistor circuits, and by using a 0.8- mu m double-metal-layer CMOS process and a low-VDD supply. The block diagram of this DSP is shown along with the mechanism of double-speed MAC operation.<>
Keywords :
CMOS integrated circuits; codecs; digital signal processing chips; linear predictive coding; 0.8 micron; 11.2 kbit/s; 16 bit; 3.5 V; 70 mW; DSP; Japan; VSELP; digital cellular standard; digital signal processor; double-metal-layer CMOS process; double-speed MAC operation; double-speed multiply-accumulate system; low-power-consumption; speech codec; vector sum-excited linear predictive; Code standards; Decoding; Digital signal processing; Digital signal processors; Energy consumption; Frequency; Registers; Speech codecs; Vectors; Viterbi algorithm;
Conference_Titel :
Solid-State Circuits Conference, 1993. Digest of Technical Papers. 40th ISSCC., 1993 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0987-1
DOI :
10.1109/ISSCC.1993.280098
