Cache miss reduction through hardware-assisted loop optimization

To reduce the miss rate of the instruction cache, a hardware-assisted loop optimization method is proposed in this paper. This method utilizes the hardware/software co-design strategy on the behavior level. Especially, this method is equipped with the specific instruction set to limit the cache misses, which can be viewed as a set of hardware for special purposes. Then based on the specific instruction set, a scheduling process is integrated which reduces the cache miss rate through the code transformation. Finally, a set of benchmarks from MediaBench1.0 are tested on the SimpleScalar platform to assist the proposed method. The final experiments indicate that 26% enhancement can be obtained for the cache miss reduction, where the specific instruction generation and the scheduling processes contribute about 23% and 3% respectively.