Title :
ESD design challenges and strategies in deeply-scaled integrated circuits
Author :
Cao, Shuqing ; Chen, Tze Wee ; Beebe, Stephen G. ; Dutton, Robert W.
Author_Institution :
Stanford Univ., Stanford, CA, USA
Abstract :
Challenges of design window shrinkage in deeply scaled silicon technologies are addressed by improving design, characterization, and modeling of I/O and ESD devices, and by developing ESD robustness and circuit performance co-design methodologies. Advanced ESD metrology methods are reviewed and their applications in providing key information for reliability modeling are investigated. Package and wafer level CDM correlation issues are examined.
Keywords :
electrostatic discharge; integrated circuit reliability; integrated circuits; ESD design challenges; deeply-scaled integrated circuits; package level CDM correlation; wafer level CDM correlation; Electrostatic discharge; VF-TLP; charged device model (CDM); co-design methodology; electrostatic discharge (ESD); field effect diode; high-speed I/O; integrated circuit reliability; semiconductor diodes;
Conference_Titel :
Custom Integrated Circuits Conference, 2009. CICC '09. IEEE
Conference_Location :
Rome
Print_ISBN :
978-1-4244-4071-9
Electronic_ISBN :
978-1-4244-4073-3
DOI :
10.1109/CICC.2009.5280727
